"Progressively" scanned television receivers have been proposed wherein the horizontal scan rate is multiplied, i.e., doubled, and each line of video is displayed twice thereby providing a displayed image having reduced visibility of line structure and subjectively improved vertical resolution. In a typical progressively scanned receiver, each line of video is stored in one of two memories. As one of the memories is being written with the incoming video signal at the standard line rate, the other memory is read two times at twice the standard line rate thereby providing two lines of time compressed video within one standard line interval. The memory output is applied to a display having a doubled horizontal sweep rate synchronized with read-out of the memory thereby doubling the number of displayed lines of video signal.
An example of a progressively scanned receiver, wherein the added video lines are not interpolated from the original scan lines, is described in U.S. Pat. No. 4,415,931 entitled TELEVISION DISPLAY WITH DOUBLED HORIZONTAL LINES which issued Nov. 15, 1983 to R. A. Dischert. A doubly scanned receiver in which the additional scan lines are obtained by interpolation from the original scan lines is described by K. H. Powers in U.S. Pat. No. 4,400,719 entitled TELEVISION DISPLAY SYSTEM WITH REDUCED LINE-SCAN ARTIFACTS which issued Aug. 23, 1983. The arrangements disclosed in these patents are incorporated by reference herein.
When implementing a progressively scanned receiver with digital signal processing circuits, one may employ random access memories (RAM) for the line stores. Digital signal processing typically utilizes a coherent clock for purposes of signal sampling (in the A/D converter), memory address control and other functions. For simplicity of chroma processing, the clock is typically phase locked to an integer multiple of the color subcarrier frequency. For NTSC standard video signals, the memory write clock frequency is typically selected to be four times that of the color subcarrier (4 fsc) or about 14.3 MHz with a period of about 70 nanoseconds. One line of memory, for this clock frequency and the standard NTSC line period of about 63.5 microseconds, therefore requires 910 locations in RAM to store 910 video samples of "pixels" (picture elements). This memory requirement is invariant for NTSC standard signal because under the NTSC standard there are exactly 227.5 color subcarrier cycles per horizontal line. With D/A conversion done at four times the color subcarrier frequency (4 fsc) there are thus, exactly 910 (4.times.227.5) pixels per line. As long as the memory read clock is exactly double the frequency of the write clock, the resultant "double-speed" or "time-compressed" pixels will have proper horizontal spacing and vertical alignment when displayed.